1. Field of the Invention
The present invention generally relates to an inter-chip or an intra-chip signal transceiver, and more particular, to a bidirectional transceiver having a differential signal transmission architecture.
2. Description of Related Art
The parasitic effects sparked by an interconnection on a chip for a very large scale integration (VLSI) would be dramatically increased with the steady progress of semiconductor process. Although the process progress is able to reduce both the width of an interconnection and the interval between interconnections, but the aspect ratio (ratio of height over width) of an interconnection must also be increased to prevent the parasitic impedance of the interconnection from significant increasing. As a whole however, the impedance of the interconnection still tends to increase as a result. Besides, as the interval between interconnections gets narrower, the coupling capacitance and the side capacitance between interconnections are increased. Thus, the parasitic capacitance or the parasitic impedance between interconnections would be increased with the advancement of the semiconductor process.
Using interconnections made of copper instead of aluminum and using a material with lower dielectric coefficient to fabricate interconnections are good solutions to reduce the parasitic effects. In addition, by inserting a buffer to delay the signal transmission on an interconnection is considered as a proper solution which is also a common design practice for an integration circuit (IC); reducing the voltage swing on an interconnection is helpful to lower the signal transmission delay and power consumption although the scheme of reducing the swing would accordingly decrease the signal driving capacity. In short, most of the circuit architectures with a lower swing fail to be operated in high frequency, which results in a slower data transmission rate.
In order to double the speed of data transmission, bidirectional signal transceiver architecture is usually preferred to transmit signals. The proposed bidirectional signal transceiver architecture on a chip is classified into two kinds: a switch-in-drain circuit architecture and a switch-in-gate circuit architectures, which are shown by FIGS. 1 and 2, respectively.
FIG. 1 is a schematic view of a switch-in-drain bidirectional signal transceiver architecture, while FIG. 2 is a schematic view of a switch-in-gate bidirectional signal transceiver architecture. In FIGS. 1 and 2, T1 and T2 represent input voltage signals, /T1 and /T2 respectively represent the inverting signals of the input voltage signals T1 and T2, O1 and O2 represent output signals, 150 represents interconnection and R represents interconnection resistance.
Since the circuit operation principle of FIG. 2 is much similar to that of FIG. 1, only the circuit operation of FIG. 1 is described hereinafter. Referring to FIG. 1, in mode for current to transmit signal, the signals of both side circuits are transmitted to one another (herein both side circuits refer to the left side circuit and the right side circuit of the interconnection 150). The transmitting terminal 110 of the left side circuit includes a set of switches 111 and 112 and a set of current sources 113 and 114, while the transmitting terminal 120 of the right side circuit includes a set of switches 121 and 122 and a set of current sources 123 and 124. By using input voltage signals to control the above-mentioned switches, the current on the interconnection 150 is varied. In the receiving terminals 130 and 140 of FIG. 1, the operations are mainly based on the scheme that replicating the current produced at the opposite transmitting terminal and then converting the current signal to a voltage signal through the technique of converting current into voltage.
The ideal signal waveforms of the two circuit architectures of FIGS. 1 and 2 are shown by FIG. 3A. In FIG. 3A, the solid line represents the voltage variation at the node W1 in FIGS. 1 and 2, while the broken line represents the voltage variation at the node W2. The operation voltage variations at the different locations of the two circuits are illustrated in FIG. 3B where the bias voltages at the different locations in the circuits of FIGS. 1 and 2 corresponding to four ideal input voltage states are listed in a table. In the table, VL=Vtn, and VH=VDD−|Vtp|, wherein Vtn represents the threshold voltage of an N-type metal oxide semiconductor transistor (NMOS transistor), while Vtp represents the threshold voltage of a P-type metal oxide semiconductor transistor (PMOS transistor).
Although the above-mentioned circuits have in the advantages of simpler architecture, but the disadvantages caused by the shortage thereof can not be ignored, because both the circuit architectures need inverters (such as 160 and 170 in FIGS. 1 and 2) to judge whether the voltages of the nodes W1 and W2 take a voltage level V1-0 or a voltage V0-1 level. Thus, the threshold voltage of the inverter must be specified between V0-1 and V1-0 by design, which requires both difference values between the threshold voltage and V0-1/V1-0 must be sufficient large for the inverter to detect the voltage levels, and accordingly lengthens the charge/discharge time of the nodes W1 and W2. As a result, the signal transmission rate is limited. On the other hand, both the two circuit architectures tend to be affected by the process (for example, affected by any electrical characteristic drift of a component), in particular, by a noise in the case where the interconnection 150 is quite long.
In more detail, the switch-in-drain circuit architecture can be classified into two kinds: a circuit architecture using diode-connected-current-sources as shown by FIG. 1 and a circuit architecture using self-bias-current-sources as shown by FIG. 4; The switch-in-gate circuit architecture can be classified into three kinds: a circuit architecture using diode-connected-current-sources as shown by FIG. 5, a circuit architecture of current-source gate-bias in ½ VDD which means the bias voltage of the current sources are set at ½ VDD as shown by FIG. 6 and a circuit architecture using terminator resistors for reducing the voltage swing as shown by FIG. 7. It is obvious that all the above-mentioned circuit architectures have the same problems, that is to say the signal transmission rate would be seriously reduced once the interconnection length is increased.